1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to an etch stop layer and method for having low dielectric constant characteristics for improving circuit performance.
2. Description of the Related Art
Dual damascene structures are employed to form both contacts to lower metal structures and metal lines simultaneously in a single deposition process. Difficulties arise in forming vias and trenches in a dielectric layer which separates the metal structures from the metal lines to be formed. Via holes are placed at needed locations where connections are to be made through the dielectric layer, while trenches are formed over greater distances for the formation of metal lines. Since the vias and trenches have different geometry, the formation of vias and trenches are formed by different patterning steps.
To accommodate the different structures, that is, vias and trenches, an etch stop layer is sandwiched between two dielectric layers. The etch stop layer is formed from a silicon nitride material. Silicon nitride is employed to permit selective etching of a first dielectric layer, which may include an oxide material, to form metal lines. Then, the nitride is etched and used to pattern vias through a second dielectric layer, which is also typically an oxide material.
The silicon nitride etch stop layer includes a dielectric constant of about 4 or 5. For metal lines having higher density, for ground rules of 0.25 microns or less, silicon nitride suffers from a high dielectric constant which may result current leakage or cross-talk between adjacent metal line or between metal lines on different layers.
Therefore, a need exists for an improved etch stop layer which provides needed selectivity to adjacent layers, provides hard mask capabilities and has a decreased dielectric constant for improving the formation of dual damascene structures.
A method for forming a dual damascene structure for a semiconductor device, in accordance with the present invention, includes providing conductive regions on a first layer, forming an interlevel dielectric layer over the first layer and forming an etch stop layer over the interlevel dielectric layer. The etch stop layer includes a polymer material having a dielectric constant of less than about 3.0. The etch stop layer is patterned to form a via pattern, and a trench dielectric layer is deposited on the etch stop layer and in holes of the via pattern. Trenches are formed in the trench dielectric layer by etching the trench layer in accordance with a trench pattern, and vias are formed in the interlevel dielectric layer by etching through the trenches using the etch stop layer to self-align the trenches to the vias and expose the conductive regions on the first layer.
In other methods, the polymer preferably includes at least one of polyorylene-ether and polybenzoxazole dielectric. The step of providing conductive regions on a first layer may includes providing one of metal lines and diffusion regions. The step of forming a cap layer on the conductive regions to protect the conductive regions from oxidation may be included.
In still other methods, the interlevel dielectric layer and the trench dielectric layer may be comprised of a same material. The same material may include one of a nitride and an oxide. The interlevel dielectric layer and the trench dielectric layer are preferably selectively etchable relative to the etch stop layer. The interlevel dielectric layer and the trench dielectric layer may also be comprised of a different material. The step of patterning the etch stop layer to form a via pattern may include employing a hard mask layer to form the via pattern. The step of depositing conductive material to concurrently form contacts in the vias and conductive lines in the trenches may be included. The step of forming an etch stop layer over the interlevel dielectric layer may include spinning on and curing the polymer. The etch stop layer may include a thickness of between about 100 nm to about 250 nm.
Another method for forming a dual damascene structure for a semiconductor device includes the steps of providing conductive regions on a first layer, forming an interlevel dielectric layer over the first layer wherein the interlevel dielectric layer included a polymer material having a dielectric constant of less than about 3.0, and forming an etch stop layer over the interlevel dielectric layer. The method further includes patterning the etch stop layer to form a via pattern, depositing a trench dielectric layer on the etch stop layer and in holes of the via pattern wherein the trench dielectric layer includes a polymer material having a dielectric constant of less than about 3.0, and forming trenches in the trench dielectric layer by etching the trench layer in accordance with a trench pattern. Vias are formed in the interlevel dielectric layer by etching through the trenches using the etch stop layer to self-align the trenches to the vias and expose the conductive regions on the first layer.
In other methods, the polymer preferably includes at least one of polyorylene-ether and polybenzoxazole dielectric. The step of providing conductive regions on a first layer includes providing one of metal lines and diffusion regions may be included. The method may include the step of forming a cap layer on the conductive regions to protect the conductive regions from oxidation. The etch stop layer may include one of an oxide and a nitride. The interlevel dielectric layer and the trench dielectric layer are preferably selectively etchable relative to the etch stop layer. The interlevel dielectric layer and the trench dielectric layer may be comprised of a different polymer material.
In still other methods, the step of forming trenches in the trench dielectric layer by etching the trench layer in accordance with a trench pattern may include the step of patterning the trench dielectric layer using an oxide layer as a hard mask. The method may further include the step of depositing conductive material to concurrently form contacts in the vias and conductive lines in the trenches. The step of forming an interlevel dielectric layer may include spinning on and curing the polymer. The step of depositing a trench dielectric layer may also include spinning on and curing the polymer.
A dual damascene structure, in accordance with the invention, includes conductive regions on a first layer, an interlevel dielectric layer formed over the first layer and having vias therethrough, a trench dielectric layer having trenches formed therein in communication with the vias and an etch stop layer formed between the interlevel dielectric layer and the trench dielectric layer. The trenches and the vias are filled with a conductive material, and the conductive material forms conductive lines in the trenches, which are connected to the conductive regions of the first layer by contacts, formed in the vias. At least one of the interlevel dielectric layer, the trench dielectric layer and the etch stop layer includes a polymer material having a dielectric constant of less than or equal to 3.0.
In alternate embodiments, the polymer may include at least one of polyorylene-ether and polybenzoxazole dielectric. The interlevel dielectric layer and the trench dielectric layer may both include the polymer material, or the etch stop layer may include the polymer material. The etch stop layer preferably includes a thickness of between about 100 nm and about 250 nm. The adjacent conductive lines may have a space of less than or equal to 0.25 microns therebetween.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.